Physical Design Engineer
MosChip®
Hyderabad, Telangana, India2h agovia LinkedIn
About the Role
The Physical Design Engineer at MosChip® will be responsible for a range of tasks in the physical design flow, from initial planning to final verification.
Key Responsibilities
- Perform top-level floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure, and ECO tasks (timing and functional ECOs).
- Conduct SI closure, design rule checks (DRC), Logical vs. Schematic (LVS) checks, and Antenna checks.
- Provide technical guidance and mentoring to physical design engineers.
- Interface with front-end ASIC teams to resolve issues.
- Achieve timing closure on DDR2/DDR3/PCIE interfaces.
- Clearly document plans.
- Prioritize work based on project needs.
Requirements & Tech Stack
- Experience with 65nm or lower node designs.
- Experience with advanced low-power techniques including Voltage Islands, Power Gating, and substrate-bias.
- Strong background in ASIC Physical Design, including:
- Floor planning
- P&R
- Extraction
- IR Drop Analysis
- Timing and Signal Integrity closure
- Expertise in Cadence, Synopsys, or Magma physical Design Tools.
- Expertise in scripting languages such as PERL and TCL.
- Strong Physical Verification skill set.
- Static Timing Analysis in Primetime or Primetime-SI.
Qualifications
- Excellent communication skills.
- Strong background of ASIC Physical Design.
- Strong Physical Verification skill set.
- Good written and oral communication skills.
- Ability to interface with different teams.