ASIC Digital Design, Engineer

About the Role

An early-career engineer opportunity to contribute to semiconductor design, specifically in formal verification.

Key Responsibilities

• Learn and apply the latest formal verification methodology to live projects.
• Execute validation as per defined plans, working with experienced formal verification engineers.
• Support quality improvements and contribute insights to enhance verification tool capabilities.
• Write and refine assertions in SystemVerilog Assertions (SVA) to capture design intent and uncover edge-case failures.
• Script verification flows using Python, Perl, or Tcl to automate tasks and improve team productivity in Unix/Linux environments.

Impact

• Help catch critical design bugs before tapeout.
• Contribute to the quality and reliability of Synopsys IP and EDA tools.
• Accelerate verification closure on complex designs using formal methods.
• Strengthen the formal verification methodology by bringing fresh perspectives and identifying gaps.

Requirements & Tech Stack

• Bachelors or Master’s degree in Electronics, Electrical, Instrumentation, or a related engineering discipline.
• 0 to 2 years of experience in digital design, verification, or related semiconductor work (internships, projects, and coursework count).
• Strong understanding of computer architecture and digital design fundamentals, including state machines, pipelining, and timing.
• Hands-on experience with hardware description languages: Verilog or SystemVerilog preferred.
• Proficiency in at least one scripting language: Python, Perl, or Tcl.
• Comfort working in Unix or Linux environments.
• Solid academic performance with relevant coursework or project work in VLSI, digital design, or verification.
• Experience with formal verification tools, assertion languages, or model checking is a strong plus.

Qualifications

• Ability to analyze block diagrams or RTL code and identify potential issues.
• Comfortable learning new tools and methodologies independently, reading documentation, and asking targeted questions.
• Clear communication of findings, including bugs, coverage gaps, or script issues.
• Detail-oriented approach to tracking down logic errors in complex designs.