Senior Lead Physical Design Engineer

About the Role

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Key Responsibilities

• Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route, etc.) on latest nodes.
• Signoff knowledge is mandatory (STA, Power analysis, FV, low power verification, PV, etc.).
• Quick learner with good analytical and problem-solving skills.
• ASIC design, verification, validation, integration, or related work experience.
• PNR implementation for Qualcomm SoC's.
• Good hands-on experience on Floorplanning, PNR and STA flows.
• Good knowledge on Placement/Clock Tree Synthesis (CTS), optimization, etc.
• Good understanding on signoff domains – LEC/CLP/PDN knowledge, etc.

Requirements & Tech Stack

• Unix/Linux – Perl/TCL fundamentals/scripting.

Qualifications

• Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• OR Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• OR PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• 5+ years Hardware Engineering experience or related work experience.
• 5+ years' experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm).