Design Verification Intern, MS

About the Role

Marvell’s semiconductor solutions are essential building blocks for data infrastructure. This internship offers the opportunity to work on technologies powering next-generation cloud, AI, storage, and networking solutions.

Your Team, Your Impact

Design Verification teams work on pre-silicon emulation and verification for ODSP-related chips, ASIC Design using UVM methodology, and powering network connectivity for data centers. You will collaborate with direct team members and cross-functional partners to deliver robust, scalable solutions.

What You Can Expect

• Dive deep into processor architecture and functionality.
• Use industry-standard tools to create simulation environments.
• Develop automated tests to identify and troubleshoot design flaws.
• Analyze test coverage results and metrics.
• Collaborate with chip architects and designers to solve complex problems.

Requirements & Tech Stack

• Currently enrolled in a Master's Degree in Electrical Engineering, Computer Engineering, or a related field.
• Expected graduation date between Fall 2027 – Summer 2028.
• Completed coursework in:
• Computer architecture
• Logic
• Processor
• Memory system
• Verilog
• VLSI
• VHDL
• UVM
• Analog
• Integrated circuit design
• Digital logic design
• SoC/ASIC design
• Verification principles
• Signals
• System and signal processing
• Proficiency in programming & scripting languages: Python, C, C++, Perl, Java.
• Experience using tools like Synopsys, Cadence, or Mentor for simulations and testbench development.
• Hands-on experience with RTL integration and bring-up systems.
• Experience with debugging complex hardware/software interactions.
• Strong analysis, problem solving, and communication skills.

Additional Information

• Pay Range (USD): $35 - $70 per hour.
• Eligible for bonus and equity plans, including new hire and annual equity grants.
• Benefits include medical, dental, and vision coverage, perks and discounts, mental health resources, and paid holidays.
• Additional compensation may be available for intern PhD candidates.
• Applicants must be eligible to access technology and/or software subject to U.S. export control laws and regulations.