ASIC Design Engineer

About the Role

Qualcomm Technologies, Inc. is seeking talented ASIC Design Engineers to contribute to the architecture, microarchitecture, design, and deployment of next-generation SoC Interconnects, Cache and Memory Subsystems, and High-Speed DDR Memory Controllers. This role involves close collaboration with architecture, verification, physical design, and software teams to develop high-performance, power-efficient silicon solutions for Qualcomm's advanced products.

Key Responsibilities

• Develop microarchitecture definitions and design specifications for complex SoC subsystems.
• Design, implement, and validate RTL for SoC interconnects, cache controllers, memory subsystems, and DDR memory controller components.
• Collaborate with system architects to evaluate hardware feasibility of new features, algorithms, and performance requirements.
• Optimize designs for performance, power, area, timing, and scalability.
• Work closely with verification teams to develop test plans, review coverage, debug issues, and achieve design quality goals.
• Support synthesis, timing closure, power analysis, gate-level simulations, and physical design activities.
• Participate in system-level integration and debugging throughout the product development cycle.
• Investigate and resolve pre-silicon and post-silicon issues.
• Contribute to C/C++ modeling, design methodologies, and process improvements.
• Collaborate across cross-functional teams to successfully deliver silicon for production.

Requirements & Tech Stack

• Experience or coursework in:
• Verilog and/or SystemVerilog RTL design
• Computer Architecture
• ASIC design methodologies
• Digital logic design
• C, C++, and/or Python programming
• Strong analytical and problem-solving skills.
• Excellent communication and collaboration skills.

Qualifications

• Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Minimum Bachelor's degree in Science, Engineering, or related field.

Preferred Qualifications

Experience or knowledge in one or more of the following areas:

• SoC interconnects and on-chip communication fabrics
• Cache and memory subsystem design
• DDR/LPDDR memory controller architecture and design
• ARM or x86 processor architectures and bus protocols
• RTL development for CPUs, cache controllers, or memory controllers
• Low-power design methodologies
• Functional verification and coverage-driven verification techniques
• Synopsys synthesis tools and ASIC implementation flows
• Timing closure, physical design support, and power optimization
• Silicon bring-up and post-silicon debug