Early Career R&D Electronics Engineer

About the Role

We are seeking a highly motivated Digital IC Design Engineer to join a collaborative team delivering advanced ASIC solutions for mission and laboratory customers. This role focuses on translating system needs into robust, verifiable RTL through tapeout, with close coordination across analog/MEMS/photonics and physical-design partners.

Key Responsibilities

• Review project schedules and milestones (tapeout targets, design reviews, lab deliverables) with the PI/tech lead, identify blockers (PDK/tool updates, interface questions, verification gaps), and drive closure.
• Convert customer/mission needs into clear block-level specifications (performance, power, area, radiation tolerance, interfaces, testability) and maintain requirements-to-design traceability.
• Develop and maintain RTL (control, datapath/DSP, interfaces), integrate IP, and implement clean CDC/reset strategies and appropriate low-power/clocking techniques.
• Build and extend verification environments; run regressions; analyze failures; close coverage; and perform lint, CDC, and formal checks with documented evidence for reviews.
• Run or coordinate synthesis and implementation handoff; review timing/power reports; debug critical paths; and iterate with physical design to meet constraints.
• Collaborate closely with analog/MEMS/photonics teams on mixed-signal interfaces (ADC/DAC timing, bias/control, sensor protocols) and validate behavior against system-level models.
• Apply knowledge of advanced integration constraints (I/O, routing, packaging, thermal, signal integrity; 2.5D/3D integration) to architecture and implementation tradeoffs.
• Incorporate resiliency features as required (TMR/EDAC, scrubbing, watchdogs, redundancy) and support radiation/reliability analysis and trade studies.
• Define scan/BIST strategy, test hooks and observability for lab bring-up, and support post-silicon debug planning and test-vector development.
• Maintain design documentation (ICDs, review packages) and present at peer reviews; capture decisions and action items for configuration control.
• Contribute to R&D efforts in advanced signal/data processing (e.g., focal-plane arrays, radiation detector readouts, neuromorphic concepts, quantum support circuits) through simulation and small test chips.
• Follow configuration management, data handling, and tool/PDK usage practices, coordinating with foundry/MPW schedules and internal processes as applicable.

Requirements & Tech Stack

• DOE Q clearance (ability to obtain and maintain)
• Verilog/SystemVerilog
• RTL design
• Synthesizable coding practices
• Digital design fundamentals (pipelining, clock-domain crossing, FSMs, datapath/control partitioning, timing closure)
• EDA toolflows for synthesis, static timing analysis (STA), linting, CDC/RDC checks, and formal verification
• CMOS device physics, digital logic, noise margins, and process technology scaling effects
• Simulation and verification using UVM or similar methodologies
• SoC integration, bus protocols (AXI/AHB/APB)
• Power aware design, low power techniques (clock gating, power gating), and PPA tradeoff analysis
• Radiation hardened design
• Ability to read and interpret schematics, timing diagrams, and physical design constraints (SDC)
• Ability to collaborate with analog, physical design, firmware, and systems teams

Qualifications

• Bachelor's degree in a relevant discipline, or an equivalent combination of directly relevant education and engineering or scientific experience.
• Demonstrated knowledge, skills, and ability to perform independent research and development.