DFT Engineer
Qualcomm
About the Role
DFT Engineer at Qualcomm
Key Responsibilities
- Responsible for RTL/GLS verification at SOC.
- Identifying issues in RTL/Netlist/Timing DBs and work with Design/PD teams.
- Working in tools Verdi and VCS for Pre Silicon verification.
- Vector generation and providing Post Silicon validation support to TE teams.
- Develop C based testcases and integrate in SV UVM environment at SOC level.
- Understand core level tests and create SOC level test plan and test cases.
Requirements & Tech Stack
- Experience in RTL/GLS verification at SOC.
- Good in Verilog/SV and familiarity with basic concepts of UVM.
- Familiarity with C-based test case bring up.
- Experience in Python/Perl or any other scripting tools.
- Knowledge in GLS/SDF debugs and problem solving.
- Knowledge in JTAG protocols and Boundary Scan architecture Verification.
- Knowledge in ARM based SOC architecture.
- Knowledge in Bus protocols (AHB, AXI, APB).
- Knowledge in Serial protocols (I2C, SPI, UART).
- Knowledge in Peripherals (USB2/3, PCIE, UFS) PHYs.
- Debugging knowledge from Assertions/waveform dumps.
- Good communication skills.
Qualifications
- Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
- OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
- OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
