Design Verification Engineer, Bangalore

About the Role

Velaura AI is seeking Design Verification Engineers to contribute to the verification and delivery of its next-generation Physical AI SoC. This role involves close collaboration with architects, RTL engineers, software engineers, and system teams to verify complex hardware blocks and system-level behavior across the platform. The goal is to ensure confidence in the correctness, performance, reliability, and safety of the architecture, from individual RTL blocks to complete HW/SW systems running real-world workloads.

Key Responsibilities

• Develop and execute verification strategies for key portions of the Velaura SoC.
• Build verification environments using SystemVerilog, UVM, C/C++, assertions, formal verification, emulation, and related methodologies.
• Collaborate with architects and RTL engineers to define verification plans, coverage goals, and correctness criteria.
• Verify compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other critical SoC infrastructure.
• Perform HW/SW co-verification involving firmware, drivers, runtime software, and operating system interactions.
• Verify performance, latency, bandwidth, QoS, and real-time system behavior under representative workloads.
• Develop assertions, checkers, scoreboards, and automated verification infrastructure.
• Participate in emulation, FPGA prototyping, and pre-silicon software bring-up activities.
• Drive bug investigation, root-cause analysis, and debug across hardware and software boundaries.
• Conduct post-silicon debug and root cause analysis.
• Leverage modern engineering tools, including AI-assisted verification workflows, to improve productivity, quality, and coverage.
• Contribute to a culture of technical excellence and continuous improvement.

Requirements & Tech Stack

• Experience verifying complex digital systems.
• Strong analytical and problem-solving skills.
• Strong understanding of computer architecture, microarchitecture, SoC architecture, and digital design fundamentals.
• Experience with SystemVerilog, UVM, C/C++, assertions, coverage-driven verification, and related methodologies.
• Familiarity with formal verification techniques and tools.
• Understanding of memory systems, interconnect fabrics, caches, DMA engines, processors, or accelerator architectures.
• Experience debugging complex system-level issues.
• Ability to work effectively in a collaborative, multidisciplinary engineering environment.

Preferred Qualifications

• Experience with one or more of the following standards: ISO 26262, IEC 61508, IEC 61511, ISO 13849.
• Experience with AI, machine learning, or edge AI hardware.
• Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
• Experience verifying QoS, latency-sensitive, or real-time systems.
• Experience with HW/SW co-verification and system-level validation.
• Exposure to performance modeling, profiling, and workload characterization.
• Experience using modern AI tools and workflows to accelerate engineering productivity.
• Background in CPUs, GPUs, AI accelerators, networking and communications silicon, storage and data movement architectures, robotics and autonomous systems, automotive and ADAS platforms, aerospace and defense systems, real-time and safety-critical computing, or functional safety architectures and methodologies.