MTS Digital Engineering

About the Role

This full-time position involves specifying, architecting, implementing, and simulating RTL components. The role is focused on DDR5 and DDR6 enterprise-class memory interface products and is within the Memory Interface Chip Business Unit. Rambus offers a flexible work environment with a hybrid approach, encouraging an average of three days per week onsite.

Key Responsibilities

• Develop System Verilog RTL IP, logic, and state machines for next-generation products.
• Perform block-level design integration and simulations to qualify behavior.
• Document design implementation with descriptions and functional diagrams.
• Estimate and track power, performance, area (PPA) tradeoffs for RTL designs.
• Collaborate with design team members to track status and ensure design implementation achieves desired outcomes.
• Review and improve Static Timing Analysis (STA) results.
• Create Verilog functional models for simulations.
• Debug verification results with the verification team.
• Support validation team during chip power-on and debug efforts.
• Perform design quality checks using CDC/RDC/LINT tools.

Requirements & Tech Stack

• Background in Digital RTL design including LEC, CDC, Lint, DFT, BIST, and STA tools.
• High aptitude with Verilog and SystemVerilog.
• Ability to document design techniques, test, and verification methodology.
• Python/perl script development.

Qualifications

• BS in Electrical Engineering with 2-3 years of experience, OR MS in Electrical Engineering or Computer Engineering with 0-1 year of experience.
• Coursework in:
• Digital Integrated Circuits
• Advanced VLSI Systems
• Advanced Computer Architecture
• Embedded Systems
• Design and Analysis of Algorithms
• Fundamentals of Machine Learning