Semiconductor Design Engineer

About the Role

The Semiconductor Design Engineer will contribute to the design, simulation, optimization, and validation of digital and analog CMOS circuits for advanced DRAM and emerging memory technologies. This role provides opportunities to work across the full product lifecycle, from early technology development through product qualification, while collaborating with global design, verification, and manufacturing teams. The successful candidate will develop technical expertise in memory design, circuit analysis, and design automation while supporting the delivery of high-quality products.

Key Responsibilities

• Design, simulate, analyze, and optimize CMOS memory circuits and functional blocks, including memory arrays, control logic, datapaths, address decoding, and input/output interfaces.
• Support physical design activities such as floor planning, placement, routing optimization, layout verification, and manufacturability improvements.
• Perform circuit simulations and debugging using industry-standard tools (e.g., FINESIM, HSPICE, VERILOG), and analyze results across operating conditions and performance targets.
• Collaborate with Product Engineering, Process Integration, Test, Assembly, CAD, Modeling, Verification, and other multi-functional partners to ensure product quality, reliability, and successful tape-out execution.
• Leverage AI Assisted design tools, Agentic AI workflows, Generative AI solutions, and automation methodologies to improve simulation efficiency, design exploration, debug processes, and engineering productivity.

Requirements & Tech Stack

• Demonstrated foundational knowledge of CMOS circuit design, semiconductor devices, and device physics.
• Experience or academic exposure to circuit simulation and modeling tools such as FINESIM, HSPICE, SPICE, or VERILOG.
• Understanding of digital logic design, state machines, and design verification methodologies.
• Strong analytical, problem-solving, written communication, and collaboration skills in a fast-paced engineering environment.
• Experience or coursework in memory design technologies such as DRAM, NAND, SRAM, high-speed circuits, or mixed-signal design.
• Familiarity with Cadence Virtuoso, physical design flows, layout methodologies, and power delivery network (PDN) analysis.
• Programming or scripting experience using Python, Tcl, Perl, or similar languages to support design automation and workflow optimization.
• Experience using AI Assisted development tools, Code Assist, LLMs, or Generative AI technologies to enhance engineering productivity, analysis, and technical problem-solving.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.