RTL Engineer Memory Subsystem, Bangalore

About the Role

Velaura AI is seeking a talented RTL Engineer to contribute to the development of our next-generation Physical AI SoC. This role focuses on the high-speed, low-power memory subsystem, essential for feeding the chip. You will collaborate with architects, performance modelers, software engineers, verification engineers, physical design teams, and memory IP/PHY partners to translate architectural concepts into production silicon. You will own significant portions of the memory subsystem design, influence microarchitectural decisions, and deliver high-performance, power-efficient hardware for intelligent physical systems.

Key Responsibilities

• Design, implement, and optimize RTL for the memory subsystem, including memory controllers, fabric interfaces, and logic integrating with external memory PHYs.
• Own memory controller and PHY integration, including interfaces like DFI, initialization and training flows, calibration, and bring-up hooks.
• Drive high-speed, low-power design of the memory path, covering timing closure, power-state management (self-refresh, power-down), clock and power gating, and DVFS interactions.
• Define hardware interfaces, memory maps, execution flows, and performance-critical interactions (scheduling, prefetching, quality of service) with software teams.
• Analyze bandwidth, latency, and utilization bottlenecks in the memory path and propose improvements.
• Optimize designs for performance, power, area, scalability, and reliability, including RAS features such as ECC and error reporting.
• Partner closely with verification and physical design teams, and with memory IP and PHY vendors during integration and silicon bring-up.
• Leverage modern engineering tools, including AI-assisted development workflows.
• Participate in design reviews and contribute to technical excellence.

Requirements & Tech Stack

• Experience designing RTL for complex digital systems, with hands-on ownership of memory subsystem blocks.
• Demonstrated experience integrating a memory controller with a memory PHY, including interfaces like DFI, initialization/training sequences, and bring-up.
• Strong understanding of high-speed, low-power memory technologies: LPDDR4, LPDDR4X, LPDDR5, LPDDR5X, DDR, and HBM, including protocol, timing, and power-state behavior.
• Strong understanding of computer architecture, microarchitecture, and digital design fundamentals.
• Expert-level Verilog and SystemVerilog skills.
• Experience with modern RTL design methodologies: lint, clock-domain crossing analysis, synthesis-aware coding, low-power intent.
• Familiarity with performance, power, and area tradeoffs in the memory path.
• Strong debugging and problem-solving skills.
• Ability to work effectively in a collaborative, multidisciplinary engineering environment.

Preferred Qualifications

• Familiarity with standard interconnect protocols like AXI, CHI, and ACE on the controller's system-side interface, including quality-of-service mechanisms.
• Experience with memory controller and PHY bring-up on silicon, including training and calibration debug and margining.
• Knowledge of reliability, availability, and serviceability (RAS) in the memory path, including inline/side-band ECC, scrubbing, poisoning, and error reporting.
• Experience with low-power design techniques and power management architectures.
• Experience developing a memory controller from the ground up, including command scheduling, arbitration, bank/rank management, refresh management, and reordering.
• Knowledge of functional safety standards such as ISO 26262 and ASIL as they apply to memory-path design.
• Experience with AI, machine learning, or edge AI hardware, especially tensor workload memory access patterns.
• Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
• Exposure to performance modeling, emulation, FPGA prototyping, or silicon bring-up.
• Experience using modern AI tools and workflows to accelerate engineering productivity.