Software R&D Engineer, VLSI Physical Design
NVIDIA
About the Role
- Develop optimization engines that fuse traditionally independent engines (e.g., co-optimization of legalization and sizing) with the objective of increasing chip frequency while minimizing power consumption across a suite of internal optimization tools.
- Improve algorithms (C++) for gate-level sizing, buffering, useful clock skew, cell legalization, power minimization, ECO routing, and incremental parasitic extraction.
- Own the whole process from discovery and invention of new optimization opportunities to developing solutions and working directly inside design teams to facilitate deployment.
Requirements & Tech Stack
- Experience with VLSI algorithms development using C++.
- Understanding of VLSI timing optimization and related concepts, including cell libraries, interconnect models, crosstalk, glitches, IR drop, timing constraints, corners, and congestion.
- Familiarity with design implementation tools such as ICC2, Innovus, PrimeTime, Tempus, and StarRC.
- Familiarity with typical design flows written in Perl, Tcl, and Python.
Ways To Stand Out
- C++14 or newer experience, such as lambdas and concurrency.
- Understanding of how multiple Physical Design steps interact and how they can potentially be fused together to form hybrid engines that result in better PPA.
- Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use.
- Experience with reinforcement learning, GNNs (Graph Neural Networks), and other relevant machine learning frameworks, especially as applied to physical design.
Qualifications
- Masters or PhD in Electrical Engineer or Computer Science (or equivalent experience).
- Proven experience in multiple areas of VLSI Physical Design Algorithms (sizing, buffering, CTS, legalization, incremental place and route etc.).
- Understanding of both software and hardware aspects.
- Creativity and self-drive to explore and perfect fast, high-capacity software.