DFT Engineer / GPU Logic Design Engineer

About the Role

As a GPU Logic Design Engineer, you will contribute to the design and validation of cutting-edge graphics IPs, including compute, display, and media units. You will be immersed in the creation of register transfer level (RTL) coding, simulation, and optimization strategies to meet power, performance, area, and timing goals. You will play a pivotal role in enabling high-quality integration of GPU blocks into larger system-on-chip (SoC) designs, directly impacting Intel's future graphics technologies.

You will be joining Intel's Data Center Group (DCG), a team dedicated to driving innovation and delivering high-performance solutions for data-centric workloads.

Key Responsibilities

• Develop logic design, RTL coding, and simulation for graphics IPs, ensuring compliance with power, performance, area, and timing requirements.
• Participate in defining architecture and microarchitecture features for GPU blocks.
• Optimize logic design to support physical implementation while maintaining design integrity.
• Review and implement verification plans to ensure design features are accurately tested across verification hierarchies.
• Drive unit-level verification and resolve RTL test failures to ensure feature correctness.
• Support SoC customers in integrating GPU blocks effectively for high-quality results.

Requirements & Tech Stack

• Demonstrated expertise in at least one of the following DFT features: TAP/JTAG, Scan/ATPG, or Array DFT (MBIST/PBIST).
• Proficiency in EDA tools such as ATPG tools, Mentor Tessent shell, VCS simulation, and debug tools.
• Experience in silicon enabling debug or test pattern development.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field with 3+ years of industry experience, OR a Master's degree in the same fields with 2+ years of industry experience, OR a PhD with no prior professional experience.
• Hybrid work model eligible.
• Primary Location: India, Bangalore.