TPU RTL Design Engineer, Cloud

About The Job

• Shape the future of AI/ML hardware acceleration by driving TPU (Tensor Processing Unit) technology.
• Develop custom silicon solutions for Google's TPU.
• Verify complex digital designs with a focus on TPU architecture and its integration within AI/ML-driven systems.
• Design SoC-level RTL for data center accelerators, focusing on chassis infrastructure, fabric bridges, and sensor telemetry networks.
• Develop infrastructure and methodology for SoCs, including error handling, debug, chip management, and SOC chassis.
• Build a global understanding of accelerator development from concept to production.
• Coordinate and co-design with software and system hardware counterparts.
• Utilize a background in RTL design to lead multi-faceted efforts.
• The AI and Infrastructure team empowers Google customers with breakthrough capabilities by delivering AI and Infrastructure at scale, efficiency, reliability, and velocity.

Key Responsibilities

• Work independently to create and review clock control subsystem's design micro-architecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with architecture and power teams to evaluate features and their impact.
• Work with Design Validation (DV) teams to create test plans to verify and debug design RTL.
• Work with physical design teams to ensure design meets physical requirements and timing closure.

Requirements & Tech Stack

• ASIC RTL design (2 years experience)
• Clocking, reset, or timing-critical RTL development
• SystemVerilog for microarchitecture specifications and synthesizable RTL
• Python, Tcl, or Perl for automating design tasks and data analysis
• Industry-standard EDA tools for simulation, synthesis, and power analysis

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture (Preferred).
• 5 years of experience with high-performance ASIC design in Phase-Locked Loop, Frequency-Locked Loop, and Delay-Locked Loop integration (Preferred).
• Experience implementing clock skipping, Dynamic Voltage and Frequency Scaling (DVFS), and fine-grained clock gating for low-power SoC optimization (Preferred).
• Knowledge of processor design or accelerators and of high-performance and low power design techniques (Preferred).
• Understanding of clock distribution challenges, including jitter, skew management, and duty-cycle distortion (Preferred).
• Proficiency in Python or Perl for automating design scripts and analyzing complex clock-tree data (Preferred).