SRAM Circuit Design Engineer

About the Role

NVIDIA is looking for a skilled and creative SRAM circuit designer to join the Digital IP (DIP) group. This group develops IP for all NVIDIA chips, working closely with internal teams to bring world-changing products to life. This is a high-visibility position focused on developing sophisticated SRAM compilers.

Key Responsibilities

• Embedded SRAM design: Transistor-level circuit design, supervising layout implementation, physical and logical verification, and debug of SRAM macros.
• SRAM compiler development: Envisioning, defining, and coding more efficient ways to automate the simultaneous assembly and validation of multiple unique SRAM macros.
• Advanced development: Exploring the potential of future process nodes and developing techniques to achieve optimal power, performance, and area characteristics.
• Guiding SOC design, silicon test, and productization efforts: Collaborate with SOC design partners, guide silicon test and characterization, and work with productization teams.

Requirements & Tech Stack

• SRAM design experience: Strong background in digital circuit design, layout, and validation on advanced FinFET and nanosheet processes.
• Design experience: In single-port, dual-port, or register file SRAM-based macros, including complex circuits such as self-timed logic and sense-amplifiers.
• Familiarity with Cadence Virtuoso schematic and layout capture tools.
• Proven delivery of silicon IP into production.

Qualifications

• Master's degree or higher in Electrical Engineering or other related field (or equivalent experience).
• Demonstrated written, verbal, and presentation skills.
• Skills in AI coding and analysis tools such as Codex and Claude Code (ways to stand out).
• Silicon testing/debug experience (ways to stand out).