Low Power ASIC Engineer

About the Role

NVIDIA is seeking a Low Power ASIC Engineer - New College Grad 2026 to join our rapidly growing research and development team focused on energy-efficient GPU and SOC architectures. You will contribute to the innovation of solutions that improve performance per watt across various sectors, powering AI, Automotive, GeForce, and Mobile products.

Key Responsibilities

• Work closely with Low Power Architecture, Design, and Software teams to understand next-generation features.
• Architect and develop testbench, infrastructure, and testplans to verify various power management solutions for NVIDIA products.
• Contribute creative ideas to improve power-aware DV methodologies.
• Influence EDA vendors to enhance simulation and debug efficiencies.

Requirements & Tech Stack

• Verilog, SystemVerilog, and UVM.
• Incisive Low-Power or Synopsys VCS NLP.
• Verdi for debugging.
• Python or PERL scripting (a plus).
• C or C++ knowledge (a plus).
• Experience writing or maintaining scripts or Makefiles for simulation program builds (a plus).

Qualifications

• Recently completed a BS, MS or PhD in Electrical or Computer Engineering, or equivalent experience.
• Understanding of low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling (DVFS).
• Good understanding of processor architecture (GPU is a plus).
• Strong debug skills.
• Prior knowledge of Low Power Architecture, Low Power CV, and deep learning (a plus).
• Good understanding of power intent in UPF format (a plus).
• Strong background in Low Power architectures or verification (a plus).