Physical Design Engineer

About the Role

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high-performance, high-quality, low-power world-class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution paths.

Key Responsibilities

• Complete ownership on PNR implementation (Floorplanning, Placement, CTS, post_route, etc.) on latest nodes.
• Signoff knowledge is mandatory (STA, Power analysis, FV, low power verification, PV, etc.).

Requirements & Tech Stack

• Good hands-on experience on Floorplanning, PNR, and STA flows.
• Good knowledge on Placement/ Clock Tree Synthesis (CTS), optimization, etc.
• Good understanding on signoff domains – LEC/CLP/PDN knowledge, etc.
• Good knowledge on Unix/Linux – Perl/TCL fundamentals/scripting.

Qualifications

• Bachelor's degree in Science, Engineering, or related field.
• 2+ years Hardware Engineering experience or related work experience.
• 2+ years' experience with PNR flow in latest tech nodes (e.g., 4nm/5nm/7nm/10nm).
• Quick learner with good analytical and problem-solving skills.