Formal Verification Engineer

About the Role

As a Formal Verification Engineer at NVIDIA, you will work in the formal verification team for the industry's leading chips. You will own the task of formal verification of RTL units for next-generation chip designs. This will involve having deep knowledge of architectural as well as micro-architectural details of the unit.

Key Responsibilities

• Developing comprehensive FV testplan documents.
• Identifying key behaviors for verification of DUT and creating a verification plan.
• Developing verification environment including environment assumptions, assertions and cover properties in context of the verification plan.
• Applying various FV techniques to prove correctness of digital designs.
• Debugging RTL to identify failure scenarios.
• Developing scripts to automate the verification process.
• Review formal setups and proofs with design and verification teams.

Requirements & Tech Stack

• BS, MS, or Ph.D. in CS/CE/EE/Mathematics or equivalent experience.
• Strong analytical skills to solve difficult problems.
• Knowledge/Experience in formal verification techniques.
• Strong knowledge of architectures of CPU/GPU designs and digital logic.
• Understanding of abstraction techniques for effective verification.
• Hands-on experience with HDLs such as Verilog / System Verilog.
• Ability to understand RTL quickly.
• Understanding of temporal logic assertions.
• Preferable experience with Formal Verification Tools (eg. Jasper, IFV, SMV, SPIN)
• Excellent communication skills with ability to work with team members and collaborate effectively.

Qualifications

• Outstanding candidates with knowledge of formal methods.
• Strong analytical skills.
• Computer architecture background.
• Experience in application of effective verification methodology.
• Deep knowledge of architectural as well as micro-architectural details of the unit.