Associate III, VLSI PD
UST
Bengaluru, Karnataka, India0–2 yrs1h agovia LinkedIn
About the Role
Associate III - VLSI PD
Key Responsibilities
- Physical design signoff
- Hierarchical & flat verification strategies
- Extraction methodologies (PEX)
Requirements & Tech Stack
- Calibre (DRC, LVS, DFM, ERC)
- ICV, Pegasus (optional but beneficial)
- Foundry rules
- Physical design signoff requirements
- Hierarchical & flat verification strategies
- Extraction methodologies (PEX)
- Proficiency in Tcl, Python, Perl for PV automation
- Experience with Design Enablement kits, tech files, runsets
Qualifications
- Strong analytical and debugging abilities
- Excellent communication and cross-functional coordination skills
- Ability to handle aggressive schedules and deliver high-quality results
- M.Tech in Electronics, VLSI, or related discipline