ASIC Engineer, Design (University Grad)

Key Responsibilities

• Architecture exploration
• Micro-architecture development
• Soft and hard IP identification, selection and integration
• Collaboration with verification and emulation teams in test plan development and debug
• Collaboration with implementation team to close the design on timing and power

Requirements & Tech Stack

• RTL development using Verilog, SystemVerilog and HLS

Qualifications

• Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta.
• Currently has, or is in the process of obtaining a PhD degree in Computer Science, Computer Engineering, a relevant technical field, and/or equivalent practical experience.
• Experience in micro-architecture and RTL development for complex control and data path IPs
• Experience in SoC micro-architecture, design and integration

Preferred Qualifications:

• Experience in data path development
• Experience in CPU, NOC, Memory and Peripheral Subsystems
• Experience with Synthesis, Timing Closure and Formal Verification Methodology