ASIC Clocks Verification Engineer

About the Role

The GPU clocks group is looking for an exceptional ASIC Clocks Verification Engineer. The team is responsible for crafting all aspects of GPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts with the floor-planning and back-end team to help craft the physical floorplan of the chip. The team explains the programming model to the SW team to come up with an efficient clock programming sequence. The team works with the silicon solution team to triage silicon or programming bugs in the lab.

Key Responsibilities

• Collaborate with other architects, ASIC designers, and verification engineers to verify high frequency clock structures.
• Engage with multiple teams and design the GPU clock structure to satisfy all architectural constraints.
• Leverage understanding of general verification principles to verify the clocks design.
• Deliver clock information to SOC verification team, timing, and DFT teams.
• Use Perl to improve the productivity of the above teams.
• Collaborate with Software and product groups to debug GPU clock silicon bugs in new products.
• Understand and design clocking structures to overcome sub-micron design challenges.
• Identify improvements in the current design and propose and implement new ways to improve the efficiency in the GPU clocking design.

Requirements & Tech Stack

• SystemVerilog
• Universal Verification Method (UVM)
• Python, Perl, or other industry-standard scripting languages.

Qualifications

• A Master’s degree in Electrical Engineering (or equivalent experience).
• Practical experience with SystemVerilog and Universal Verification Method (UVM).
• Experience with Design Verification, Logic Design, and Logic Synthesis.
• Strong coding skills in Python, Perl, or other industry-standard scripting languages.