STA Staff Engineer

About the Role

Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Key Responsibilities

• Define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development.
• Collaborate with cross-functional groups to determine product execution path.
• Experience in static timing analysis, constraints and other physical implementation aspects.
• Prepare complex ECOs for timing convergence [across huge set of corners] through Tweaker / Tempus / Physical PT ECOs.
• Minimize power.
• Push PPA to the best possible extent.

Requirements & Tech Stack

• Static timing analysis
• Constraints
• Physical implementation aspects
• Industry standard tools: PT, Tempus, GENUS, Innovus, ICC
• STA fixing aspects for critical timing bottleneck paths
• ECOs for timing convergence
• Power minimization techniques
• Perl
• TCL

Qualifications

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• 8+ years of experience in static timing analysis, constraints and other physical implementation aspects.
• Solid understanding of industry standard tools PT, Tempus, GENUS, Innovus, ICC.
• Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths.
• Experienced in preparing complex ECOs for timing convergence [across huge set of corners] through Tweaker / Tempus / Physical PT ECOs.
• Aware of tricks for minimizing power.
• Experience in deep submicron process technology nodes is strongly preferred.
• Knowledge of high performance and low power implementation methods is preferred.
• Willing to push PPA to the best possible extent.
• Strong fundamentals.
• Expertise in Perl, TCL language.