Memory IP Design Engineer

About the Role

Synopsys is a leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. This role focuses on memory IP design for real products.

Key Responsibilities

• Design and simulate embedded memory circuits including SRAM, ROM, and Register Files using Cadence Virtuoso and related tools.
• Support layout activities by working with layout engineers to ensure design intent translates cleanly into physical implementation.
• Run bitcell characterization and basic reliability analysis to validate performance across process, voltage, and temperature corners.
• Debug circuit-level issues by analyzing simulation results, identifying root causes, and proposing fixes with guidance from senior engineers.
• Collaborate with CAD, verification, and frontend teams to align on design requirements, timing constraints, and integration needs.
• Characterize the memory compiler for desired PPA (Performance, Power, Area).
• Use scripting in C-Shell, Perl, or Python to automate repetitive tasks and improve design flow efficiency.

Requirements & Tech Stack

• Cadence Virtuoso or similar tools for schematic capture, simulation, and layout interaction.
• Scripting in C-Shell, Perl, or Python.
• Embedded memory design: SRAM, ROM, or Register Files.
• Understanding of memory architectures, bitcell design, and circuit fundamentals including read/write operations and sense amplifier behavior.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical field.
• 0 to 2 years of hands-on experience in CMOS circuit design, specifically with embedded memory such as SRAM, ROM, or Register Files.
• Experience using Cadence Virtuoso or similar tools.
• Exposure to scripting languages like C-Shell, Perl, or Python is a plus.
• Ability to analyze simulation waveforms and identify anomalies.
• Proactive in seeking clarification on unclear requirements.
• Capability to manage multiple design tasks in parallel.
• Adaptability to learning new tools and methodologies.