ASIC Floorplan Design Engineer

About the Role

NVIDIA is seeking a talented ASIC Floorplan Design Engineer to design and implement the world’s leading SoC's and GPU's. This position offers an opportunity to craft and influence the design and development of the next generation GPU and SoC.

Key Responsibilities

• Work with architects, design leads, physical design leads, and package leads to develop and optimize floorplans during early chip development.
• Drive the area review process and collaborate with the ASIC design team to identify opportunities for area, interconnect, and floorplan improvements.
• Solve timing and routing congestion issues by influencing early design and physical implementation decisions with the physical and ASIC design teams.
• Build tools and improve existing infrastructure to optimize chip area and speed of execution.

Requirements & Tech Stack

• Experience in Verilog, System Verilog, or similar HVL.
• Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R, and timing closure.
• Python, Perl, and C/C++ programming language experience.

Qualifications

• Masters Degree in Electrical Engineering, Computer Science, or Computer Engineering or equivalent experience.
• A deep hardware engineering background with a concentration in VLSI and/or Computer Architecture.
• Strong communication and interpersonal skills and ability & desire to work as a great teammate.

Ways To Stand Out

• Experience in driving development of large scale ASIC floorplan is a huge plus.