AMS Verification Engineer

Position: Research & Development – RF, Analog and Mixed Signal – AMS Verification Engineer – II

Key Responsibilities

• AMS Verification (80%)
• Develop and execute verification plans for AMS IPs and subsystems, primarily involving ADCs, DACs, PLLs, and mixed-signal interfaces.
• Build AMS verification environments using SystemVerilog, Verilog-AMS, Real Number Modeling (RNM), and UVM-MS methodologies.
• Create behavioral models for analog blocks and validate functionality against specifications.
• Perform mixed-signal simulations and regression activities across different corners and operating modes.
• Define and track functional coverage and verification metrics for AMS designs.
• Collaborate closely with Analog Design, Modeling, and Validation teams for comprehensive verification closure.
• Analyze simulation failures, root-cause issues, and drive resolution with design teams.
• Support IP and SoC level integration verification activities.
• Digital Verification (20%)
• Develop and maintain UVM-based verification components and testbenches.
• Create test scenarios, assertions, scoreboards, monitors, and checkers.
• Perform protocol and interface verification for digital control logic associated with ADC/DAC IPs.
• Work on coverage closure, regression analysis, and debug activities.
• Contribute to automation and methodology improvements.

Requirements & Tech Stack

• SystemVerilog
• Verilog-AMS
• Real Number Modeling (RNM)
• UVM-MS
• UVM
• ADCs
• DACs
• PLLs

Note: Face-to-face interview is mandatory. Laptop collection will be from Noida location, with the initial work location in Bangalore.