NOC Design Verification Sr Lead Engineer

About the Role

• Qualcomm is a leading technology innovator pushing the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all.
• As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world-class products.
• Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Key Responsibilities

• Responsible for Verification of next generation Infrastructure IPs (DDRSS, Memory Controllers) for System-on-chip (SoC).
• Plan and implement IP/Cluster/Formal verification flows for Infra IPs.
• Coordinate with different Design and SOC teams throughout the IP development cycle.
• Ownership of DV test bench and associated collaterals (Checkers, Trackers, Scoreboards, Assertion, Functional Coverage).
• Develop test plan and test cases to cover design feature set.
• Follow up with stakeholders on code coverage and functional coverage closure at different test bench levels.
• Work closely with System Architects, Design, and emulation teams on failure debugs and coverage closure.
• Debug of regression signatures and identifying bug fixes.
• Responsible for Quality sign-off and required documentation.
• Develop/Deploy scripts/tools for validation (Certitude, VC Formal, VPlan).
• Debug and root-cause post-silicon issues in collaboration with Design, SW, and test teams.
• Work with the SoC level performance modeling team on latency and bandwidth analysis.

Requirements & Tech Stack

• UVM based verification expertise.
• Knowledgeable about ARM bus protocols, Virtual Memory concepts, SoC system architecture.
• Experience in developing Monitors, Scoreboards, Sequencers utilizing scripts, System Verilog, UVM.
• Methodologies to increase the rate of bug finding and resolution.
• Scripting languages (Python or Perl) for Automation initiatives.
• C/C++/SystemC for performance models.
• Post-silicon bring-up and HW-SW debug experience is a plus.
• Knowledge and exposure to silicon debug tool chains is an added advantage.

Qualifications

• Bachelor/Master’s Degree in Electronics & Communication / Micro Electronics.
• 3+ Years of Experience in IP verification or related.
• Experience with UVM and ARM Bus protocols.

Additional Skills

• Strong debugging, analytical, and problem-solving skills.
• Communication and collaboration skills to work with a large, world-wide design organization.

Desired Skills

• Experience in designs optimized for low power (Dynamic clock gating, Logic/Memory power collapse).
• Experience in verifying designs meeting Automotive Safety Integrity Levels (ASIL).