Senior DFT Engineer

About the Role

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Key Responsibilities

• ASIC/DFT development

Requirements & Tech Stack

• In-depth knowledge of DFT concepts
• In-depth knowledge and hands-on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis
• Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations
• Expertise in scripting languages such as perl, shell, etc.
• Experience in simulating test vectors
• Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TK, TetraMax)
• Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus
• Ability to work in an international team, dynamic environment
• Ability to learn and adapt to new tools and methodologies
• Ability to do multi-tasking & work on several high-priority designs in parallel
• Excellent problem-solving skills
• Excellent communication and team work skills
• Good English is required

Qualifications

• Bachelor's degree in Science, Engineering, or related field.