Campus Hiring
MAXVY Technologies Pvt Ltd
Tirunelveli, Tamil Nadu, IndiaFresher3d agovia LinkedIn
About the Role
This is a Design Verification Engineer Trainee role for MAXVY's campus hiring program, targeting the 2027 graduating batch.
Key Responsibilities
- Undergo technical training on essential skills for VLSI Design Verification.
- Learn the fundamentals of digital electronics and VLSI design concepts.
- Develop basic knowledge of Verilog and SystemVerilog.
- Understand programming fundamentals and logical problem-solving techniques.
- Learn the basics of functional verification and testbench development.
- Gain exposure to simulation tools and waveform analysis.
- Work closely with the Design Verification team under expert guidance.
- Assist in developing and executing test cases and verification scenarios.
- Participate in debugging, issue analysis, and verification activities.
- Complete practical assignments and projects to strengthen technical skills.
Requirements & Tech Stack
- Verilog
- SystemVerilog
- Digital Electronics
- VLSI Design
- Functional Verification
- Testbench Development
- Simulation Tools
- Waveform Analysis
Qualifications
- Education: B.E, M.E, M.Tech, B.Tech
- Minimum 75% throughout education with no history of arrears.
Location & Onboarding
- Job Location: Bengaluru / Tirunelveli
- Training Location: Tirunelveli (1 year)
- Relocation: Must be willing to relocate to Bangalore based on project needs within 1 year of training.
- Onboarding Process:
- Online documentation upon selection.
- 10-day awareness program at Tirunelveli.
- 90 working days unpaid Academic internship in Tirunelveli.
- Joining date after results (will not be confirmed if any history of arrears is found).
Compensation & Agreement
- Salary: 4 LPA (3 LPA base + 1 LPA retention bonus)
- Service Agreement: 4 years