DFT Engineer

Qualcomm

Noida, Uttar Pradesh, India2+ yrs4h agovia LinkedIn

About the Role

As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world-class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Key Responsibilities

  • Plan, design, optimize, verify, and test electronic systems, circuits, and related hardware.
  • Ensure bring-up yield for developed hardware.
  • Design and verify DFT (scan/mbist) insertion.
  • Generate and verify ATPG patterns.
  • Verify MBIST.
  • Perform post-silicon bring-up and yield analysis.
  • Define test mode timing constraints.
  • Provide timing fixes and corrective actions for timing violations.
  • Analyze and devise new tests for new technologies, custom RAM designs, RMA, etc.
  • Simulate test vectors.
  • Work in an international team and dynamic environment.
  • Multi-task and work on several high-priority designs in parallel.

Requirements & Tech Stack

  • DFT
  • ATPG
  • Scan Insertion
  • MBIST
  • JTAG
  • DFT insertion, ATPG pattern generation/verification, MBIST verification
  • Test mode timing constraints
  • Scripting languages (e.g., Perl, Shell)
  • Simulating test vectors
  • Equivalence check
  • RTL lint tools (e.g., Spyglass)

Qualifications

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
  • Minimum of 2+ years’ experience in the area of DFT, ATPG, Scan Insertion, MBIST, JTAG.
  • In-depth knowledge of DFT concepts.
  • In-depth knowledge and hands-on experience in DFT(scan/mbist) insertion, ATPG pattern generation/verification, mbist verification and post silicon bring up/yield analysis.
  • Expertise in test mode timing constraints definition.
  • Knowledge in providing timing fixes/corrective actions for timing violations.
  • Ability to analyze and devise new tests for new technologies/custom RAM design/RMA etc.
  • Expertise in scripting languages such as Perl, Shell, etc.
  • Experience in simulating test vectors.
  • Knowledge of equivalence check and RTL lint tool (like Spyglass).
  • Ability to work in an international team, dynamic environment.
  • Ability to learn and adapt to new tools and methodologies.
  • Ability to do multi-tasking & work on several high priority designs in parallel.
  • Excellent problem-solving skills.

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