Campus Hiring
MAXVY Technologies Pvt Ltd
MAXVY - Campus Hiring - 2027
Location: Bangalore, Tirunelveli
Role: Design Verification Engineer Trainee
Key Responsibilities
- Undergo technical training on essential skills required for VLSI Design Verification.
- Learn the fundamentals of digital electronics and VLSI design concepts.
- Develop basic knowledge of Verilog and SystemVerilog.
- Understand programming fundamentals and logical problem-solving techniques.
- Learn the basics of functional verification and testbench development.
- Gain exposure to simulation tools and waveform analysis.
- Work closely with the Design Verification team under expert guidance.
- Assist in developing and executing test cases and verification scenarios.
- Participate in debugging, issue analysis, and verification activities.
- Complete practical assignments and projects to strengthen technical skills.
Requirements & Tech Stack
- Verilog
- SystemVerilog
- Digital Electronics
- VLSI Design Concepts
- Programming Fundamentals
- Logical Problem-Solving Techniques
- Functional Verification
- Testbench Development
- Simulation Tools
- Waveform Analysis
Qualifications
- B.E, M.E, M.Tech, B.Tech
- 75% throughout education and no history of arrears.
Job Location: Training at Tirunelveli (1 year), with willingness to relocate to Bangalore based on project needs within that year. Work will then be in Bengaluru for 3 years.
Salary: 4 LPA (3 LPA base + 1 LPA retention bonus).
Service Agreement: 4 years.
Onboarding Process: Online documentation upon selection, 10 days awareness program at Tirunelveli, 90 working days unpaid Academic internship in Tirunelveli. Joining date contingent on results and no history of arrears. Offer letter issued upon completion of Academic Internship.
Interview Process: Written Test (Aptitude, Digital Electronics, Verilog - MCQ format), Technical Discussion, HR Discussion.