Engineer, ASIC Digital Design

About the Role

As an ASIC Digital Design Engineer, you will contribute to the design and development of RTL for next-generation DRAM memory controllers and subsystems. You will work in a collaborative engineering environment supporting design implementation, simulation, validation, and chip bring-up activities while leveraging AI-enabled tools to improve productivity and design quality.

Key Responsibilities

• Design and develop RTL for DRAM memory controllers and subsystem components using SystemVerilog.
• Collaborate with analog, verification, physical design, validation, and other cross-functional teams to support successful product development.
• Develop and validate HDL models, support simulation and co-simulation activities, and analyze design functionality and performance.
• Support chip bring-up, debugging, and validation activities to identify and resolve design issues.
• Use scripting, automation, and AI-enabled tools to improve design workflows, productivity, and engineering efficiency.

Requirements & Tech Stack

• SystemVerilog
• Python, Linux Shell, or similar tools for software programming, scripting, or automation.
• AI-enabled tools and large language models (LLMs) such as Copilot, Claude, or similar technologies.

Qualifications

• 0-2 years of relevant experience through internships, research, academic projects, or industry experience in digital design, ASIC development, RTL design, or related engineering fields.
• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Knowledge of digital logic design and RTL development using SystemVerilog.
• Understanding of verification methodologies, high-speed digital interfaces, and ASIC development principles.
• Basic understanding of analog and mixed-signal concepts such as PLLs, DLLs, CDRs, CMOS, or high-speed interface design.
• Strong written and verbal communication skills with the ability to collaborate effectively across engineering teams.

Preferred Qualifications

• Experience with DRAM interfaces, memory controller design, or memory-system reliability concepts.
• Familiarity with industry-standard ASIC development tools for synthesis, linting, equivalency checking, formal verification, or simulation.
• Experience supporting silicon bring-up, lab validation, debugging, or root-cause analysis activities.
• Experience developing automation solutions, engineering scripts, or workflow improvements using Python or related technologies.
• Demonstrated interest in applying AI-assisted tools and workflows to improve engineering productivity, design quality, or debug efficiency.
• Proven ability to learn quickly, solve complex technical problems, and contribute effectively in a collaborative engineering environment.