Intern

About the Role

This is an on-site internship role in San Jose, California, within the Cadence DDR IP group for a Post-Silicon Validation Engineering Intern. Local candidates will be considered.

Key Responsibilities

• Validating system-level and electrical performance of internal silicon test chips.
• Debugging silicon issues in close collaboration with analog and digital design teams.
• Delivering high-quality characterization reports.
• Working cross-functionally to ensure product functionality, reliability, and successful deployment.
• Driving system and electrical testing efforts for identifying silicon issues.
• Being involved in debug efforts for silicon issues.

Requirements & Tech Stack

• Analog and digital electronics
• RTL
• Signal integrity
• Control systems
• Analytical and problem-solving skills
• Python, C or other scripting tools (for script-based test automation) - a plus

Qualifications

• Currently pursuing a Bachelor's or Master’s degree in electrical engineering.
• Excellent written and verbal communication skills.
• Ability to work collaboratively in a team environment.
• Prior experience in the hardware semiconductor or electronics industry - a plus.
• Ability to prove full-time hours availability in San Jose during the Fall.
• Legal authorization to work in the US.