FPGA Electrical Engineer I

About the Role

The Multi-Product Power & Digital department is responsible for FPGA and hardware designs for electronic warfare, radar, and effector products.

Key Responsibilities

• Work onsite at our Fort Wayne, IN Location.
• Provide Full Lifecycle support of production quality FPGA.
• Generate FPGA Designs.
• Design and Code in VHDL for reliability and maintainability.
• Create complete documentation including requirements, verification plan, and users guides.
• Troubleshooting electronics in a lab or production environment.
• Performing system and circuit level analysis.
• Supporting failure investigations.
• Maintaining and creating documentation.
• Hardware and/or logic design.
• Interacting with multi-discipline groups including suppliers.

Requirements & Tech Stack

• FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding).
• Experience with AMD (Xilinx), Altera and/or Microchip (Microsemi) devices.
• Experience with tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.
• Hands-on experience with integration and debug of FPGA/ASIC in a lab environment.
• Experience with source code management, design reviews, and code release in a team development environment.

Qualifications

• Bachelors degree in Electrical Engineering, Computer Engineering or related Science, Technology, Engineering, or Mathematics (STEM) major.
• The ability to obtain and maintain a U.S. government issued security clearance is required.
• U.S. citizenship is required.
• DoD Clearance: Secret Active and existing security clearance required after day 1.

Preferred Qualifications

• Demonstrated experience with VHDL or Verilog coding, simulation, and synthesis.
• Knowledge of electrical circuit design, analysis and troubleshooting using common lab equipment.
• FPGA/ASIC design experience in one or more of the following areas:
• Embedded systems design using ARM, Microblaze, or NIOS processors.
• Gigabit serial interfaces and multi-gigabit transceivers (MGTs).
• Constrained random verification in UVM using System Verilog.
• Experience with High Level Synthesis (HLS).
• Experience with vector processors and/or GPUs.
• Experience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.
• Demonstrated ability to lead design efforts and/or small teams.