ASIC Engineer Intern, Design Verification

About the Role

Meta is seeking an ASIC Engineer Intern to join our Infrastructure organization. This role involves participating in the design and verification of advanced IPs using state-of-the-art tools, and building accelerators for top workloads to enable data center scaling.

Key Responsibilities

• Develop tests, checkers, and coverage to aid in design verification.
• Gain understanding of design architecture and microarchitecture.
• Utilize SystemVerilog/UVM/C code to generate test content.
• Develop scripts for process automation.
• Debug test failures and collaborate with design, verification, and modeling teams to resolve issues.
• Contribute to the improvement of verification processes and methodology.

Requirements & Tech Stack

• Knowledge of Computer Architecture and Logic Design fundamentals.
• Experience in critical and creative thinking for design verification and problem-solving.
• Proficiency in SystemVerilog/VHDL/Verilog/UVM.
• Scripting experience with Python or Perl.

Qualifications

• Must obtain and maintain work authorization in the country of employment.
• Intent to return to a degree program after the internship.
• Internships are twelve (12) to sixteen (16) weeks long.