Formal Verification Engineer

Mirafra Technologies

Key Responsibilities

• Perform high-quality pre-silicon verification tasks to target high-quality silicon with no functional bugs.
• Develop Specman E and SystemVerilog UVM compliant verification environments.
• Perform formal verification of IPs (e.g., DMA, NVM FSMs).
• Create verification plans and execute coverage closure.
• Provide relevant reports to show progress.
• Run regressions, help set up automatic regressions, and debug failures.
• Drive debugging.
• Run verification environments quality checks with Certitude and improve the environment to reach ASIL-D level for the verification environment.

Requirements & Tech Stack

• SystemVerilog UVM
• Cadence JasperGold
• Certitude
• Xcelium
• Vmanager Enterprise edition
• System Verilog
• VHDL
• Basic knowledge of scripting languages – perl / python
• Tools: Cadence JasperGOLD, Xcelium, Vmanager Enterprise edition, System Verilog, VHDL, perl / python, Certitude

Qualifications

• Proven working experience within the semiconductor industry in constraint random functional and formal verification.
• Expertise in hardware verification using SystemVerilog UVM.
• Expertise in formal verification using Cadence JasperGold.
• Knowledge of using regression and coverage analysis tools.
• Knowledge of test bench qualification.
• Working experience in international and cross-functional technical teams within a multi-cultural environment.
• Excellent English communication skills.

Deliverables

• Test cases ready for regression.
• Plans for reaching defined verification KPIs.
• Qualified verification environment using formal verification tools.
• Intermediate reports and debug of failing test cases, coverage gap analysis.
• Verification sign-off report fulfilling defined KPIs (e.g., 100% coverage).