ASIC Design Verification Engineer I (Full Time)
Cisco
About the Role
As an ASIC Engineer, you will play a critical role in developing Cisco’s revolutionary data center solutions. You will collaborate closely with verification engineers, designers, hardware, and other cross-functional teams to verify the ASIC in simulation, in emulation, and during ASIC bring-up to help guarantee seamless integration and optimal performance of Cisco’s hardware platforms.
Key Responsibilities
- Maintaining existing DV environments and enhancing them
- Construct test bench including scoreboard, agents, sequencers, and monitors for new blocks
- Write test plan, develop test cases, debug regression failures, and drive to module verification closure
- Ensuring complete verification coverage through implementation and review of code and functional coverage
Requirements & Tech Stack
- System Verilog
- UVM methodology
- Perl and/or Python scripting
- Experience with Veloce/HAPS (preferred)
- Experience building test benches from scratch, including experience in SystemVerilog constraints, structures, and classes (preferred)
Qualifications
- A Bachelor's degree (completed within the past 3 years or expected to be completed within the next 12 months).
- Qualifying education and work experience should be in ASIC Design, Design Verification, or a related field.
- Qualifying education and work experience should be in ASIC Engineering, Verification, or a related field.
- Experience with System Verilog and UVM methodology.
- Experience with scripting using Perl and/or Python.
- Experience using UVM and SystemVerilog for ASIC verification and verifying complex blocks and/or clusters within ASICs (preferred).
- Experience with functional coverage and constrained random DV environments (preferred).
- Experience in verifying complex blocks, clusters, and top-level for SoC (preferred).
- Effective verbal and written communication skills.