Process Integration Development Engineer

About the Role

Intel's Logic Technology Development (LTD) is seeking a Process Integration Development Engineer specializing in Defect Metrology. This role is central to developing new silicon process technologies, enabling the transition from research to high-volume manufacturing while maintaining high-quality standards. As part of the Manufacturing Integration Engineering (MIE) organization, you will drive yields on advanced processes by reducing defects to best-in-class targets.

Key Responsibilities

• Identify all defects impacting yield and performance in advanced silicon process technologies.
• Characterize processes using cutting-edge metrology tools.
• Investigate root cause owners and develop defect reduction roadmaps to meet program milestone commitments.
• Collaborate with process modules and integration teams to drive roadmaps by developing and qualifying process fixes through Model-Based Problem Solving (MBPS).
• Respond to defect baseline shifts to isolate root causes and implement preventative actions using 8D methodology.
• Own a segment of the process to ensure adequate metrology is in place to detect and respond to all yield-limiting defects before end-of-line sort.
• Investigate and respond to exclusionary baseline shifts to restore segment defect health to capable, demonstrated baselines.
• Develop new recipes and RFCs as part of New Product Introduction (NPI).
• Provide navigation and leadership to meet Intel's yield objectives using state-of-the-art metrology tools and test vehicles (QTM, Short Loop, etc.).
• Organize and present defect summaries to F25, LTD, and MDCE engineering teams.
• Partner with Intel Integration, Yield, and failure analysis labs to provide root causes for all defect issues.
• Hold the team and collaborators accountable for quality through Integrated Module Team (IMT) and Focus Team (FT) forums.
• Work collaboratively as part of the overall LTD Defect metrology group.
• Role-model and establish a team culture of trust, collaboration, safety, accountability, and sustaining excellence.
• Build strong relationships with other LTD teams based on mutual trust and respect.

Requirements & Tech Stack

• Strong data analysis and problem debug skills.
• Team player with flexibility and adaptability to changing business needs.
• Strong ownership mindset and driving closure.
• Excellent communication and navigation skills to larger audiences.
• Understanding and adherence to Intel cultural values.
• Experience obtained through a combination of prior education, classes, projects, research, and relevant previous job and internship experience.

Qualifications

Minimum Qualifications

• Master's degree in Materials Science and Engineering, Electrical Engineering, Chemical Engineering, Mechanical Engineering, Physics, Nuclear Engineering, Optics, Chemistry, or Computer Science.
• Hands-on experimental research experience: designing and conducting experiments, operating laboratory equipment (characterization, fabrication, or synthesis), and analyzing statistical data.

Preferred Qualifications

• Demonstrated academic research, coursework, laboratory, or internship experience with one or more of the following:
• Materials characterization (SEM, TEM, AFM, etc.), materials fabrication, synthesis, metrology, statistical or data analysis (MATLAB, Excel, JMP, Python, etc.).
• Semiconductor processing fundamentals (lithography, wet and/or dry etch, chemical mechanical polishing, thin films), semiconductor and/or transistor device physics, and Design of Experiments (DOE).
• Defect metrology, defect inspection/improvement, yield analysis, or process integration.
• Demonstrated application of Statistical Process Control (SPC) or Design of Experiments (DOE) principles.
• Complex problem-solving methodologies: root cause analysis, Model-Based Problem Solving (MBPS), 5 Why, Fishbone diagrams, or 8D frameworks.
• Understanding of semiconductor physics or semiconductor processing cleanroom unit operations.
• Understanding of defect metrology tools such as brightfield, darkfield, or voltage contrast (VC).