MTS, Analog Layout

About the Role

• Lead full-custom layout for complex Analog / Mixed‑Signal IP blocks.
• Own layout quality from floor-planning to tape-out.
• Work closely with circuit designers to translate performance goals into layout strategies.
• Provide technical guidance and design reviews for junior and mid-level layout engineers.
• Establish and document best-known methods (BKMs) for AMS layout across nodes.
• Drive IP reuse, layout template development, and methodology improvements.

Key Responsibilities

• Technical Ownership
• Layout for complex Analog / Mixed‑Signal IP blocks, including:
• Bandgap references, LDOs and regulators, Charge pumps (positive/negative)
• PLLs, delay lines, oscillators, IO & PHY‑related analog blocks
• Temperature sensors, bias circuits
• ESD protection devices and clamps
• Ensure layout quality:
• Device matching and symmetry, noise isolation and substrate strategies
• Robust power/ground planning
• Yield, reliability, and DFM compliance
• Especially in noise-sensitive mixed-signal environments.
• Advanced Technology Expertise
• Experience in advanced FinFET nodes such as TSMC 3nm, 5nm.
• Fin quantization awareness
• Multi‑Vt, multi‑fin strategies
• Advanced metal stack planning
• Solid background in planar CMOS technologies (e.g., 40nm, 65nm, 90nm).
• Deep understanding of foundry PDKs, layout‑dependent effects (LDEs), and process variability.
• Layout Verification & Signoff
• Drive and close DRC, LVS, ERC, ANTENNA, and reliability checks.
• Review and address issues related to:
• EM/IR, latch‑up, ESD window compliance
• Device stress and matching degradation
• Interface with foundry and CAD teams for waiver management and signoff convergence.
• AI usage proficiency
• Strong understanding of AI/ML and Generative AI concepts.
• Proficiency in Python/scripting and EDA automation to develop AI-assisted layout and verification solutions.
• Ability to translate layout expertise into constraints, algorithms, datasets, and measurable optimization objectives.
• Experience developing, integrating, and validating AI-driven methodologies against traditional designer-driven flows.

Requirements & Tech Stack

• Advanced FinFET nodes such as TSMC 3nm, 5nm.
• Planar CMOS technologies (e.g., 40nm, 65nm, 90nm).
• Foundry PDKs.
• DRC, LVS, ERC, ANTENNA, and reliability checks.
• EM/IR, latch‑up, ESD window compliance.
• AI/ML, Generative AI.
• Python/scripting.
• EDA automation.

Qualifications

• Technical Ownership of complex Analog / Mixed‑Signal IP blocks.
• Experience in advanced FinFET nodes and planar CMOS technologies.
• Deep understanding of foundry PDKs, LDEs, and process variability.
• Proficiency in AI/ML and Generative AI concepts.
• Proficiency in Python/scripting and EDA automation.
• Experience developing, integrating, and validating AI-driven methodologies.