VLSI Logic Design Intern

About the Role

• This role is designated as 'Hybrid', requiring an average of 2 days per week working from an HPE office.
• The HPE Cray Slingshot team develops backbone technologies for high-performance supercomputers, presenting complex design challenges.

Key Responsibilities

• Assist with VLSI / RTL design using System Verilog.
• Assist with creating System Verilog Assertions (SVAs) and utilize Formal Verification to prove design correctness.
• Assist with writing coverage to measure stimulus quality and perform coverage analysis to identify verification holes.
• Assist with creating scripts (Python, TCL, Perl) to improve design processes and efficiency.

Requirements & Tech Stack

• Working toward a Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, or equivalent.
• System Verilog experience for synthesis (ASIC or FPGA).
• Proficiency in electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture.
• Experience in executive written and verbal communication skills; mastery in English.
• Ability to work with cross-functional teams (DV/Arch/Design/FW).
• Self-driven with a positive, can-do attitude, and detail-oriented.

Preferred Skills

• Understanding of the OSI model for layered networking stacks.
• Experience with Ethernet protocols, CPU or GPU systems, and high-speed peripherals.
• Understanding of Formal Verification concepts and design verification using UVM.
• Working knowledge of C/C++ or Python scripting.