Physical Design Engineer

About the Role

• Full-time, on-site role based in Bengaluru.
• Focus on implementing and optimizing chip-level physical design.
• Work in a dynamic engineering and innovation-focused environment.
• Collaborate with RTL, logic, circuit, and architecture teams.

Key Responsibilities

• Implementing and optimizing chip-level physical design, including floorplanning, placement, clock tree synthesis, routing, and timing closure.
• Working with RTL and logic design teams to understand design intent.
• Running physical verification checks, addressing DRC, LVS, and other signoff issues.
• Collaborating with circuit and architecture teams to balance performance, power, and area.
• Preparing design documentation.
• Supporting tape-out activities.
• Participating in design reviews.
• Contributing to tool and flow improvements.
• Maintaining robust methodologies for physical implementation.

Requirements & Tech Stack

• Physical Design (e.g., floorplanning, placement, routing, timing closure)
• Physical Verification (e.g., DRC, LVS, signoff tools)
• Logic Design and RTL Design
• Circuit Design concepts (understanding of performance, power, and area trade-offs)
• Proficiency with industry-standard EDA tools (e.g., Cadence, Synopsys, Mentor)
• Solid understanding of VLSI design flows, timing analysis, and low-power design techniques.

Qualifications

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• Strong analytical and problem-solving abilities.
• Attention to detail.
• Capability to work collaboratively in a team-oriented environment.