ASIC Engineer Intern, Implementation

About the Role

Meta is seeking an ASIC Engineer Intern to join our Infrastructure organization. You will be an integral member of an ASIC team to build accelerators for top workloads, enabling data centers to scale efficiently. You will have the opportunity to participate in design implementation/emulation, physical design, EDA infrastructure methods, and design power estimation/management using state-of-the-art tools. Internships are twelve (12) to sixteen (16) weeks long.

Key Responsibilities

• Participate in Design Implementation, Physical Design, and Design Power reviews and provide feedback.
• Contribute to optimizing RTL for IPs to achieve best PPA (Power, Performance, Area), and support implementation and physical design.
• Develop scripts, tools, and methods to enhance PPA (Power, Performance, Area).
• Support and develop EDA Infrastructure, and help improve designer productivity.
• Support Simulation accelerators and post-Silicon validation.

Requirements & Tech Stack

• Knowledge of Verilog, VHDL, or HLS.
• Knowledge of Computer Architecture and Logic Design fundamentals.
• Experience with Lint, Synthesis, Formal or Physical Design tools.
• Scripting capability with Python or Perl.
• Experience with High Performance Computing.
• Experience with Digital Signal Processing Techniques.
• Creativity and problem-solving capabilities.

Qualifications

• Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment.
• Intent to return to degree-program after the completion of the internship.