Trainee Engineer

About the Role

As a Trainee Engineer - Digital Design Verification on the Silicon Engineering team, you will work on Graphics /Security IP, ensuring the functional correctness of complex, next-generation architecture. You will learn from industry experts and gain hands-on experience building advanced simulation and emulation testbenches using industry-standard methodologies.

Key Responsibilities

• Testbench Development: Assist in developing, maintaining, and enhancing block-level and chip-level simulation testbenches (TB).
• UVM Architecture: Write scalable verification components, including drivers, monitors, predictors, and scoreboards using SystemVerilog (SV) and UVM.
• Emulation Platforms: Collaborate with senior engineers to bring up emulation testbenches for hardware-accelerated verification and pre-silicon validation.
• Graphics IP Verification: Learn the intricate architecture of Graphics IPs (pipelines, shaders, or memory controllers) and map out comprehensive verification plans.
• Debug & Coverage: Run regressions, debug hardware failures using waveform viewers, and write functional coverage covergroups to achieve 100% verification closure.

Requirements & Tech Stack

• Languages: Strong foundational knowledge of SystemVerilog (SV).
• Methodology: Exposure to UVM (Universal Verification Methodology) through university coursework, lab projects, or internships.
• Core Concepts: Solid understanding of digital logic design, computer architecture, and FIFO/arbitration mechanisms.
• Scripting: Basic proficiency in scripting languages like Python, Perl, or Bash for automation.

Qualifications

• Education: Bachelor’s or master’s degree in Electronics Engineering, Computer Engineering, Computer Science, or a related field (Graduation date within the last 12 months).

Preferred Qualifications (Bonus)

• Prior internship experience in ASIC/FPGA design or verification.
• Direct project experience involving Graphics IP, GPU architectures, or high-throughput data pipelines.
• Familiarity with hardware emulation platforms (e.g., Palladium, Zebu, Veloce) or FPGA prototyping.
• Experience with EDA tools from Synopsys, Cadence, or Siemens (e.g., VCS, Questa, Xcelium).