Senior Lead STA Engineer

About the Role

Qualcomm is a leading technology innovator pushing the boundaries of what's possible to enable next-generation experiences and drive communication and data processing transformation. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power world-class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Key Responsibilities

• Define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development.
• Collaborate with cross-functional groups to determine product execution path.
• Perform static timing analysis, constraints, and other physical implementation aspects.
• Address STA fixing aspects to solve extreme critical timing bottleneck paths.
• Prepare complex ECOs for timing convergence across a huge set of corners through Tweaker / Tempus / Physical PT ECOs.
• Minimize power.
• Push PPA to the best possible extent.

Requirements & Tech Stack

• Static Timing Analysis
• Constraints
• Physical Implementation
• STA fixing
• ECOs (e.g., through Tweaker, Tempus, Physical PT ECOs)
• Power minimization
• PPA optimization
• Perl
• TCL
• PT
• Tempus
• GENUS
• Innovus
• ICC
• Deep submicron process technology nodes
• High performance and low power implementation methods

Qualifications

• Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• OR Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
• OR PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.
• Desired Experience:
• 5+ years of experience in static timing analysis, constraints and other physical implementation aspects.
• Solid understanding industry standard tools PT, Tempus, GENUS, Innovus, ICC.
• Solid grip on STA fixing aspects to solve extreme critical timing bottleneck paths.
• Experienced about preparing complex ECOs for timing convergence [across huge set of corners] through Tweaker / Tempus / Physical PT ECOs.
• Aware about the tricks for minimizing power.
• Experience in deep submicron process technology nodes is strongly preferred.
• Knowledge of high performance and low power implementation methods is preferred.
• Strong fundamentals.
• Expertise in Perl, TCL language.