Ph.D. Intern

About the Role

Marvell's analog design team creates the essential building blocks for data infrastructure. As a Ph.D. Intern, you will work on challenging circuit design problems at the physical limits of silicon, contributing to production IP and research-stage silicon within active design teams. This program embeds doctoral candidates directly into these teams, focusing on projects at the intersection of Marvell's engineering challenges and doctoral research in electrical engineering. You will experience the complete design flow, from architecture to silicon bring-up, and participate in a structured analog design curriculum.

What You Can Expect

As our Ph.D. Analog Design Intern, you will:

• Design, simulate, and verify analog and mixed-signal circuit blocks across the full design flow: architecture, schematic, simulation, layout coordination, and silicon bring-up.
• Work on production-grade IP, including:
• High-speed SerDes building blocks
• Silicon Photonics driver and receiver circuits
• ADC/DAC architectures
• PLLs
• Clock distribution networks
• LDOs
• Other precision analog circuits in advanced CMOS FinFET processes.
• Utilize industry-standard tools such as Cadence and MATLAB.
• Collaborate directly with layout engineers for design implementation and iteration based on feedback.
• Attend and contribute to design reviews with the engineering team.
• Present your work, including research framing and design results, to engineers.
• Participate in a structured analog design curriculum alongside peers.

What We're Looking For

To thrive in this role, you must have experience designing analog and mixed-signal circuits at the transistor level. Specifically:

• Currently enrolled in a Ph.D. program in Electrical Engineering or a related field, with a research focus in analog, mixed-signal, or RF circuit design.
• Demonstrate hands-on experience designing and simulating analog circuit blocks such as PLLs, SerDes building blocks, ADCs, DACs, LDOs, amplifiers, or high-speed I/O.
• Apply strong fundamentals in transistor-level circuit design, including device physics, noise analysis, linearity, stability, and low-power techniques in advanced CMOS processes.
• Independently simulate and verify designs using industry-standard tools like Cadence Virtuoso and Spectre.
• Experience with MATLAB or Python for system-level modeling is a plus.
• Communicate design decisions and tradeoffs clearly.

Preferred Qualifications

• Experience designing in FinFET process nodes (7nm, 5nm, 3nm, or equivalent).
• Familiarity with high-speed serial link architectures, optical transceiver circuits, or Die-to-Die interconnect design.
• Exposure to layout-aware design, parasitic extraction, or post-layout simulation.
• Experience with behavioral modeling in Verilog-A or similar.

Compensation & Benefits

• Expected Base Pay Range (USD): $38 - $76 per hour.
• Eligibility for Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers.
• Intern benefits include:
• Medical, dental, and vision coverage
• Perks and discounts
• Robust mental health resources
• Paid holidays.
• Additional compensation may be available for intern Ph.D. candidates.