R&D DSP/FPGA Design Automation Intern

About the Role

We are seeking a motivated R&D intern to help develop and demonstrate a scalable, AI-assisted development workflow for FPGA-based digital signal processing systems. This position is well suited to a student who enjoys working across traditional boundaries between signal processing, digital design, and software development. You will gain experience with a complete FPGA development lifecycle while investigating how AI-assisted engineering can improve development speed, reuse, and consistency without replacing sound engineering judgment.

Key Responsibilities

• Build reusable, parameterized FPGA components for DSP, such as MACs, FIFOs, adder trees, coefficient memories, delay elements and numeric conversion blocks.
• Translate DSP and system requirements into FPGA architecture and implementation specs.
• Design and verify RTL in Verilog, SystemVerilog, VHDL or an equivalent language.
• Write bit-accurate or fixed-point reference models to check the FPGA implementations against.
• Assemble the components into a representative streaming DSP subsystem.
• Create automated simulation and verification tests that cover numerical accuracy, reset behavior, streaming interfaces, backpressure and parameter boundaries.
• Support synthesis, timing analysis, resource evaluation and optimization.
• Use Python or a similar language to automate design, testing, data collection and reporting.
• Investigate AI-assisted development tools across FPGA architecture, implementation, verification and documentation. Define objective ways to measure the quality of their output.
• Analyze results and identify functional, numerical, timing or resource limitations.
• Collaborate with DSP, FPGA, software and system engineers, including in design reviews.
• Document interfaces, parameter constraints, verification results and findings.
• Present results and recommendations to the engineering team at the end of the internship.

Requirements & Tech Stack

• Coursework, project work or job experience in DSP or digital system design.
• Understanding of digital logic, synchronous design, pipelining and FSMs.
• Experience with at least one HDL or hardware-construction language (Verilog, SystemVerilog, VHDL or Chisel).
• Experience with Python, MATLAB, C/C++ or a similar language for modeling or automation.
• Familiarity with fixed-point arithmetic, quantization or numerical implementation of DSP algorithms.
• Ability to turn requirements into an implementable design.
• Ability to analyze technical results and communicate conclusions clearly.
• Strong problem-solving, communication and teamwork skills.
• Ability and desire to learn emerging technologies.

Qualifications

• Currently pursuing a Bachelor's or Master's in EE, CE, CS or a related field.

Desired

• Experience designing, simulating or synthesizing FPGA logic, with Xilinx/AMD, Intel or comparable tools.
• Experience with streaming interfaces (valid/ready, FIFOs, clock domains).
• Experience implementing FIR filters, resamplers, channelizers or other waveform processing.
• Experience writing parameterized, reusable HDL.
• Experience with cocotb, constrained-random testing, assertions or formal verification.
• Experience with Git, CI, automated builds or regression testing.
• Experience building software tools for other engineers.
• Experience using AI-assisted tools for software, HDL, testing or analysis.
• Familiarity with component metadata, interface contracts, model-based design or digital twins.
• Interest in FPGA tradeoffs among throughput, latency, timing and DSP, memory and logic resources.