Chip Design Integration Engineer

About the Role

At IBM Infrastructure & Technology, you will design, develop, test, and deliver offerings for Power & Z using the latest technologies. You will define the physical design and lay out the chip footprint, ensuring that all design constraints are met.

Key Responsibilities

• Design, develop, test, and deliver offerings for Power & Z, defining the physical design and laying out the chip footprint.
• Perform Chip Integration: Interconnect all circuits, arrays, random logic, and I/O on the chip to a given set of ground rules for the silicon technology selected.
• Verify Design Constraints: Perform a series of checks (software runs) to verify that all design constraints are met, utilizing toolsets such as Cadence or other proprietary tools.
• Manage Chip Footprint: Define the physical design and lay out the chip footprint, ensuring effective use of space and meeting design requirements.

Requirements & Tech Stack

• Chip Design Development: Experience with designing, developing, testing, and delivering offerings for Power & Z, including defining physical designs and laying out chip footprints.
• Chip Integration Engineering: Experience in interconnecting circuits, arrays, random logic, and I/O on chips to meet ground rules for selected silicon technologies.
• Design Constraint Verification: Experience with performing software runs to verify design constraints, utilizing toolsets such as Cadence or other proprietary tools.
• Silicon Technology Application: Experience applying knowledge of silicon technologies to ensure effective chip design and integration.
• Physical Design Optimization: Experience with optimizing physical designs to meet space and performance requirements.

Preferred Education: Master's Degree

Preferred Technical And Professional Experience

• Familiarity with proprietary tools for performing software runs to verify design constraints is beneficial.
• Understanding of various silicon technologies and their application in chip design and integration is advantageous.
• Familiarity with principles of physical design optimization to meet space and performance requirements is desirable.