SOC Power Architecture Engineer

About the Role

Qualcomm provides complete chipset solutions. Power is a key area that drives the value of our chips. As fabrication technology node shrinks, and performance requirements become higher, it is crucial to provide power-optimized solutions. This role is responsible for on-target power optimization feature prototyping and waveform analysis.

Key Responsibilities

• On Target power optimization feature prototyping and waveform analysis
• Develop novel power optimized multi-media HW and Systems architecture for next generation SOCs
• Implement models for power projections, validation and architectural trade off analysis
• Establish use-case and HW core power targets
• Work with HW/SW design teams to implement and validate power features and targets through various design stages from concept to implementation

Requirements & Tech Stack

• Solid foundation in Electrical Systems Engineering and Digital Logic Design
• Solid understanding of HW micro-architecture of digital systems with the understanding of ASIC implementation flow from concept to production
• Knowledge of system level aspects of low power design and the ability to model and analyze power at system and core level
• Experience with video encoder/decoder systems and architecture
• Experience with camera systems and architecture
• Experience in power modeling, verification, and simulation tools
• Experience with high level synthesis tools and flow
• Competitive analysis and Machine Learning workload analysis experience is a bonus

Qualifications

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field.