GPU Physical Design Engineer (Senior/Lead)

Qualcomm

Bengaluru, Karnataka, India2+ yrs58m agovia LinkedIn

About the Role

Qualcomm's GPU team is seeking experienced Physical Design Engineers to drive implementation and physical signoff of next-generation high-performance GPU designs. The role involves close collaboration with RTL, STA, DFT, Power, and SoC teams to achieve aggressive PPA targets and successful tapeouts.

Key Responsibilities

  • Physical Implementation activities for high performance GPU Core, including Floor-planning, Place and Route, CTS, Formal verification, Physical Verification (DRC/LVS), PDN, Timing Closure, and power optimization.
  • Drive implementation of PPA critical Cores and make PPA trade-off decisions.
  • Achieve timing convergence of high frequency data-path intensive Cores using advanced STA concepts.
  • Collaborate with design, DFT, and PNR teams to resolve issues related to constraints validation, verification, STA, and Physical design.
  • Handle technical deliverables within a small team of engineers.

Requirements & Tech Stack

  • Physical Implementation
  • Floor-planning
  • Place and Route (PnR)
  • Clock Tree Synthesis (CTS)
  • Formal Verification
  • Physical Verification (DRC/LVS)
  • Power Delivery Network (PDN)
  • Timing Closure
  • Power Optimization
  • Synopsys ICC2 or Cadence Innovus
  • PrimeTime SI (PTSI) or Tempus
  • Tcl/Perl Scripting
  • Advanced STA Concepts
  • Clocking Architecture

Qualifications

  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
  • OR Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
  • OR PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
  • 3+ years of experience in Physical Design/Implementation.
  • Strong expertise in timing convergence of high frequency data-path intensive Cores.
  • Good understanding of clocking architecture.
  • Strong problem-solving skills.
  • Good communication skills.
  • Experience working as part of a larger team and working towards project milestones and deadlines.

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