Student Intern, Research

About the Role

Join Nokia Bell Labs in Bangalore as an Intern focused on advanced computing architectures and algorithms for next-generation communication systems. This internship involves enabling energy-efficient AI and wireless communication workloads through hardware-aware AI algorithms, neuromorphic computing, and domain-specific hardware acceleration, with potential exploration of RISC-V-based accelerators. You will work across AI/ML, wireless signal processing, energy-efficient computing, and hardware/software co-design, developing concepts and running experiments in Python and C.

Key Responsibilities

• Explore research ideas related to energy-efficient compute for AI-driven wireless communication systems.
• Study and evaluate neuromorphic computing approaches and their applicability to wireless workloads.
• Develop experimental prototypes, models, and benchmarks using Python and C.
• Explore accelerator concepts, including RISC-V-based acceleration, custom instruction extensions, or hardware/software co-design approaches.
• Potentially contribute to Verilog implementation, microarchitecture exploration, or architecture-level design and simulation.
• Compare conventional AI compute approaches with low-power, event-driven, approximate, or neuromorphic compute techniques.
• Evaluate compute and energy-efficiency trade-offs.

Requirements & Tech Stack

• Enrolled in a Ph.D. or MS Research program at the time of the internship.
• Hands-on programming experience in Python and/or C.
• Availability for a 6-month internship.

Qualifications

• Strong background in one or more areas such as computer architecture, VLSI/digital design, AI/ML algorithms, wireless communications, signal processing, embedded systems, or hardware/software co-design.
• Ability to design experiments, analyze results, and iterate on research ideas independently.
• Strong fundamentals in algorithms, digital systems, and performance/energy trade-off analysis.

Nice to have:

• Exposure to RISC-V architecture, instruction-set extensions, accelerator design, or processor microarchitecture.
• Interest or experience in neuromorphic computing, spiking neural networks, event-driven compute, or low-power AI.
• Familiarity with energy-efficient computing techniques such as quantization, sparsity, approximate computing, pruning, or workload-specific acceleration.
• Understanding of RTL design, hardware simulation, or FPGA/ASIC design flows.