RISC V based Fabless SOC Design Engineering Intern

About the Role

The RISC-V based Fabless SOC Design Engineering Intern will support the design, verification, and documentation of SOC architectures and subsystems based on the RISC-V instruction set. This is a full-time, on-site role located in Bhubaneswar, providing hands-on experience in fabless SOC development within an embedded and cloud-focused environment.

Key Responsibilities

• Assist in hardware design and integration activities.
• Collaborate with engineers on system-level modeling.
• Help with simulation, testing, and validation of SOC components.
• Work closely with cross-functional teams to understand requirements.
• Review design specifications.
• Contribute to design improvements and optimization.

Requirements & Tech Stack

• Ability to read technical documentation.
• Experience with EDA tools or simulators (preferred).
• Experience working with Linux-based development environments.

Qualifications

• Skills in Design Engineering and Product Design.
• Strong interest in SOC architecture and RISC-V-based systems.
• Skills in Mechanical Engineering and Computer-Aided Design (CAD) for understanding enclosure, thermal, and mechanical aspects of SOC-based products.
• Skills in Electrical Engineering for circuit-level understanding, hardware integration, and board-level design considerations.
• Strong foundation in electronics, digital design, computer architecture, or related disciplines.
• Coursework or projects in RISC-V, SOC, or embedded systems are highly beneficial.
• Effective communication, collaboration, and problem-solving skills.
• Ability to learn quickly in a fast-paced engineering environment.
• Pursuing or having recently completed a degree in Electrical/Electronics Engineering, Computer Engineering, or a related technical field.